Universal Remote Control R7 - SPECS SHEET User Manual Page 10
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ADP5589 Data Sheet
Rev. B | Page 10 of 52
KEY
SCAN
CONTROL
1
2 3
4
5 6
7
8 9
VDD
R0 R1
R2C2C0
C1
3 × 3 KEYPAD MATRIX
09714-008
Figure 9. Simplified Key Scan Block
Figure 9 shows a simplified representation of the key scan block
using three row and three column pins connected to a small
3 × 3, nine-switch keypad matrix. When the key scanner is idle,
the row pins are pulled high and the column pins are driven
low. The key scanner operates by checking the row pins to see
if they are low.
If Switch 6 in the matrix is pressed, R1 connects to C2. The key
scan circuit senses that one of the row pins is pulled low, and a
key scan cycle begins. Key scanning involves driving all column
pins high, then driving each column pin, one at a time, low and
sensing whether a row pin is low or not. All row/column pairs are
scanned; therefore, if multiple keys are pressed, they are
detected.
To prevent glitches or narrow press times being registered as a
valid key press, the key scanner requires the key be pressed for
two scan cycles. The key scanner has a wait time between each
scan cycle; therefore, the key must be pressed and held for at
least this wait time to register as being pressed. If the key is
continuously pressed, the key scanner continues to scan, wait,
scan, wait, and so forth.
If Switch 6 is released, the connection between R1 and C2
breaks, and R1 is pulled up high. The key scanner requires that
the key be released for two scan cycles because the release of a
key is not necessarily in sync with the key scanner, it may take
up to two full wait/scan cycles for a key to register as released.
When the key is registered as released, and no other keys are
pressed, the key scanner returns to idle mode.
For the remainder of this document, the press/release status of a
key is represented as simply a logic signal in the figures. A logic
high level represents the key status as pressed, and a logic low
represents released. This eliminates the need to draw individual
row/column signals when describing key events.
KEY x KEY RELEASED KEY RELEASED
KEY PRESSED
09714-009
Figure 10. Logic Low: Released; Logic High: Pressed
Figure 11 shows a detailed representation of the key scan block
and its associated control and status signals. When all row and
column pins are used, a matrix of 88 unique keys can be
scanned.
- ADP5589 1
- TABLE OF CONTENTS 2
- SPECIFICATIONS 3
- ABSOLUTE MAXIMUM RATINGS 5
- QUICK DEVICE OVERVIEW 7
- 9714-004 7
- DEVICE ENABLE 8
- DEVICE OVERVIEW 8
- EVENT FIFO 9
- KEY SCAN CONTROL 9
- Rev. B 10
- KEY PRESSED 10
- 09714-009 10
- Data Sheet ADP5589 11
- ADP5589 Data Sheet 12
- Key Pad Extension 12
- Ghosting 12
- FIFO Lock/Unlock 12
- GPI Input 15
- REGISTER INTERFACE 19
- REGISTER MAP 21
- ID Register 0x00 23
- INT_STATUS Register 0x01 23
- Status Register 0x02 23
- FIFO_1 Register 0x03 24
- Rev. B 25
- Rev. B 26
- GPI_INT_STAT_A Register 0x13 27
- GPI_INT_STAT_B Register 0x14 27
- GPI_INT_STAT_C Register 0x15 27
- GPI_STATUS_A Register 0x16 28
- GPI_STATUS_B Register 0x17 28
- GPI_STATUS_C Register 0x18 28
- RPULL_CONFIG_A Register 0x19 29
- RPULL_CONFIG_B Register 0x1A 29
- RPULL_CONFIG_C Register 0x1B 30
- RPULL_CONFIG_D Register 0x1C 30
- RPULL_CONFIG_E Register 0x1D 31
- GPI_EVENT_EN_A Register 0x21 32
- GPI_EVENT_EN_B Register 0x22 33
- GPI_EVENT_EN_C Register 0x23 33
- DEBOUNCE_DIS_A Register 0x27 35
- DEBOUNCE_DIS_B Register 0x28 35
- DEBOUNCE_DIS_C Register 0x29 36
- GPO_DATA_OUT_A Register 0x2A 36
- GPO_DATA_OUT_B Register 0x2B 36
- GPO_DATA_OUT_C Register 0x2C 37
- GPO_OUT_MODE_A Register 0x2D 37
- GPO_OUT_MODE_B Register 0x2E 37
- GPO_OUT_MODE_C Register 0x2F 38
- UNLOCK1 Register 0x33 39
- UNLOCK2 Register 0x34 39
- EXT_LOCK_EVENT Register 0x35 39
- UNLOCK_TIMERS Register 0x36 40
- LOCK_CFG Register 0x37 40
- RESET1_EVENT_A Register 0x38 40
- RESET1_EVENT_B Register 0x39 40
- RESET1_EVENT_C Register 0x3A 41
- RESET2_EVENT_A Register 0x3B 41
- RESET2_EVENT_B Register 0x3C 41
- RESET_CFG Register 0x3D 41
- PWM_OFFT_LOW Register 0x3E 42
- PWM_OFFT_HIGH Register 0x3F 42
- PWM_ONT_LOW Register 0x40 42
- PWM_ONT_HIGH Register 0x41 42
- PWM_CFG Register 0x42 42
- CLOCK_DIV_CFG Register 0x43 43
- LOGIC_1_CFG Register 0x44 43
- LOGIC_2_CFG Register 0x45 43
- LOGIC_FF_CFG Register 0x46 44
- POLL_TIME_CFG Register 0x48 44
- PIN_CONFIG_A Register 0x49 45
- PIN_CONFIG_B Register 0x4A 45
- PIN_CONFIG_C Register 0x4B 45
- PIN_CONFIG_D Register 0x4C 46
- GENERAL_CFG_B Register 0x4D 46
- INT_EN Register 0x4E 47
- APPLICATION DIAGRAM 48
- OUTLINE DIMENSIONS 49
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