Universal Remote Control R7 - SPECS SHEET User Manual Page 18
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ADP5589 Data Sheet
Rev. B | Page 18 of 52
RESET_PULSE_WIDTH[1:0]
RESET_TRIGGER_TIME[2:0]
RESET1_EVENT_A[7:0]
RESET1_EVENT_B[7:0]
RESET1_EVENT_C[7:0]
KEY
SCAN
CONTROL
RST_PASSTHRU_EN
RST
(R4)
RESET1
GPI
SCAN
CONTROL
LOGIC
BLOCK
CONTROL
RESET2_EVENT_A[7:0]
RESET2_EVENT_B[7:0]
(C4)
RESET2
RESET1_
INITIATE
RESET2_
INITIATE
RESET
GEN 2
RESET
GEN 1
09714-024
Figure 25. Reset Blocks
The RESET1 signal uses I/O Pin R4 as its output. A pass-
through mode allows the main
RST
pin to be output on the
R4 pin also.
The RESET2 signal uses I/O Pin C4 as its output.
The reset generation signals are useful in situations where the
system processor has locked up and the system is unresponsive
to input events. The user can press one of the reset event combina-
tions and initiate a system-wide reset. This alleviates the need
for removing the battery from the system and performing a
hard reset.
It is not recommended to use the immediate trigger time (see
the details of the RESET_CFG Register, 0x3D, in Table 69)
because this setting may cause false triggering.
INTERRUPTS
The
INT
pin can be asserted low if any of the internal interrupt
sources is active. The user can select which internal interrupts
interact with the external interrupt pin in register INT_EN
(Address 0x4E, Bits[7:0]) (refer to Table 86). allows the user to
choose whether the external interrupt pin remains asserted, or
deasserts for 50 µs, then reasserts, in the case that there are
multiple internal interrupts asserted, and one is cleared (refer
to Table 85).
EVENT_INT
EVENT_IEN
INT DRIVE
INT
INT_CFG
GPI_INT
GPI_IEN
LOGIC1_INT
LOGIC2_INT
LOGIC1_IEN
LOGIC2_IEN
OVRFLOW_INT
OVRFLOW_IEN
LOCK_INT
LOCK_IEN
09714-025
Figure 26. Asserting
INT
Low
- ADP5589 1
- TABLE OF CONTENTS 2
- SPECIFICATIONS 3
- ABSOLUTE MAXIMUM RATINGS 5
- QUICK DEVICE OVERVIEW 7
- 9714-004 7
- DEVICE ENABLE 8
- DEVICE OVERVIEW 8
- EVENT FIFO 9
- KEY SCAN CONTROL 9
- Rev. B 10
- KEY PRESSED 10
- 09714-009 10
- Data Sheet ADP5589 11
- ADP5589 Data Sheet 12
- Key Pad Extension 12
- Ghosting 12
- FIFO Lock/Unlock 12
- GPI Input 15
- REGISTER INTERFACE 19
- REGISTER MAP 21
- ID Register 0x00 23
- INT_STATUS Register 0x01 23
- Status Register 0x02 23
- FIFO_1 Register 0x03 24
- Rev. B 25
- Rev. B 26
- GPI_INT_STAT_A Register 0x13 27
- GPI_INT_STAT_B Register 0x14 27
- GPI_INT_STAT_C Register 0x15 27
- GPI_STATUS_A Register 0x16 28
- GPI_STATUS_B Register 0x17 28
- GPI_STATUS_C Register 0x18 28
- RPULL_CONFIG_A Register 0x19 29
- RPULL_CONFIG_B Register 0x1A 29
- RPULL_CONFIG_C Register 0x1B 30
- RPULL_CONFIG_D Register 0x1C 30
- RPULL_CONFIG_E Register 0x1D 31
- GPI_EVENT_EN_A Register 0x21 32
- GPI_EVENT_EN_B Register 0x22 33
- GPI_EVENT_EN_C Register 0x23 33
- DEBOUNCE_DIS_A Register 0x27 35
- DEBOUNCE_DIS_B Register 0x28 35
- DEBOUNCE_DIS_C Register 0x29 36
- GPO_DATA_OUT_A Register 0x2A 36
- GPO_DATA_OUT_B Register 0x2B 36
- GPO_DATA_OUT_C Register 0x2C 37
- GPO_OUT_MODE_A Register 0x2D 37
- GPO_OUT_MODE_B Register 0x2E 37
- GPO_OUT_MODE_C Register 0x2F 38
- UNLOCK1 Register 0x33 39
- UNLOCK2 Register 0x34 39
- EXT_LOCK_EVENT Register 0x35 39
- UNLOCK_TIMERS Register 0x36 40
- LOCK_CFG Register 0x37 40
- RESET1_EVENT_A Register 0x38 40
- RESET1_EVENT_B Register 0x39 40
- RESET1_EVENT_C Register 0x3A 41
- RESET2_EVENT_A Register 0x3B 41
- RESET2_EVENT_B Register 0x3C 41
- RESET_CFG Register 0x3D 41
- PWM_OFFT_LOW Register 0x3E 42
- PWM_OFFT_HIGH Register 0x3F 42
- PWM_ONT_LOW Register 0x40 42
- PWM_ONT_HIGH Register 0x41 42
- PWM_CFG Register 0x42 42
- CLOCK_DIV_CFG Register 0x43 43
- LOGIC_1_CFG Register 0x44 43
- LOGIC_2_CFG Register 0x45 43
- LOGIC_FF_CFG Register 0x46 44
- POLL_TIME_CFG Register 0x48 44
- PIN_CONFIG_A Register 0x49 45
- PIN_CONFIG_B Register 0x4A 45
- PIN_CONFIG_C Register 0x4B 45
- PIN_CONFIG_D Register 0x4C 46
- GENERAL_CFG_B Register 0x4D 46
- INT_EN Register 0x4E 47
- APPLICATION DIAGRAM 48
- OUTLINE DIMENSIONS 49
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